The telecommunications industry continually attempts to improve the transmitter circuitry in wireless communication systems. Power amplifier (PA) circuitry is a major component of a transmitter of a wireless communication device. Power amplifier (PA) circuitry provides the power for transmitting a signal (including data modulated and carried by the signal) so that a base station or a receiver can receive the signal.
Power amplifier (PA) circuitry uses a large amount of power. The power amplifier (PA) module is one of the most power consuming components of a wireless communication device. Therefore it is very desirable to provide power amplifier (PA) circuitry that is power efficient.
One method for improving power amplifier (PA) efficiency is to use a drain/collector modulation technique. In the drain/collector modulation technique a non-linear high efficiency power amplifier can be used (e.g., a class C power amplifier) instead of a linear low efficiency power amplifier (e.g., a class A amplifier). The power control of the power amplifier (PA) circuitry is achieved by adjusting the power amplifier (PA) power supply VCC. A high efficiency power supply combined with a high efficiency power amplifier (PA) (with constant bias) would be ideal.
In prior art power amplifier (PA) modules in GSM (Global System for Mobile Communications) telecommunication devices such as RF3110 (manufactured by RFMD) and TQM7M4014 (manufactured by Triquint), the power amplifier (PA) power supply VCC is from a linear regulator or “low drop out” (LDO) circuit. An LDO circuit can have a high efficiency when the value of its output voltage (VCC) is near the value of its input voltage (VBATT). But an LDO circuit will have a very low efficiency when its output voltage (VCC) is very low compared with its input voltage (VBATT).
The maximum efficiency for an LDO circuit is the ratio of the output voltage VCC to the input voltage VBATT. That is, the maximum efficiency is given by the ratio VCC/VBATT. For example, the maximum efficiency for an LDO in a typical GSM handset with an output voltage of nine tenths volts (VCC=0.9 volts) and an input voltage of three and six tenths volts (VBATT=3.6 volts) is twenty five percent (25%).
FIG. 1 illustrates a schematic diagram of a first prior art power supply control circuit 100. Power supply control circuit 100 comprises a low drop out (LDO) circuit 110. Low drop out (LDO) circuit 110 comprises an operational amplifier 120 that receives a VRAMP signal on its inverting input. A feedback voltage signal VFB is provided to the non-inverting input of operational amplifier 120. The operating voltage for low drop out (LDO) circuit 110 is provided by a voltage source VBATT.
The output of operational amplifier 120 is provided to a gate of a PMOS transistor 140. The source of PMOS transistor 140 is coupled to the operating voltage VBATT. The drain of PMOS transistor 140 is coupled to a first end of a first resistor 150. The second end of first resistor 150 is coupled to a first end of a second resistor 160. The second end of second resistor 160 is coupled to ground. The feedback voltage signal VFB is obtained from a node between the first resistor 150 and the second resistor 160.
The output of low drop out (LDO) circuit 110 is the power supply voltage VCC. A capacitor 170 is coupled between the output of the low drop out (LDO) circuit and ground. The power supply voltage VCC is provided to radio frequency (RF) power amplifier (PA) 130. Radio frequency (RF) power amplifier (PA) 130 amplifies an RF input signal (RFIN) to generate an amplified RF output signal (RFOUT).
One method for increasing the efficiency of the power amplifier (PA) power supply VCC is to use a switching regulator. A switching regulator is able to adjust the value of the operating voltage (designated VSWITCHER) that is provided to a low drop out circuit. FIG. 2 illustrates a schematic diagram of a second prior art power supply control circuit 200 that comprises a switching regulator 210 (designated “switcher 210”). Switcher 210 has a first input that receives a peak value of voltage (designated VPEAK) and a second input that receives an enable signal (designated ENSWITCHER).
The low drop out circuit 110 in FIG. 2 has the same structure as the low drop out circuit 110 shown in FIG. 1. However, the operation of the low drop out circuit 110 in FIG. 2 no longer has a single value of operating voltage VBATT. Instead, switcher 210 provides a wide dynamic range of operating voltages VSWITCHER to the low drop out circuit 110. For example, the value of the operating voltage VSWITCHER may be chosen in a range from about four hundred millivolts (400 mV) to about four and eight tenths volts (4.8 V).
FIG. 3 illustrates a schematic diagram of a third prior art power supply control circuit 300. Power supply control circuit 300 comprises a switching regulator 304 (designated “switcher 304”) and a low drop out (LDO) circuit 306. As shown in FIG. 3, switcher 304 low drop out (LDO) circuit 306 both receive the VRAMP voltage. Both switcher 304 and low drop out (LDO) circuit 306 also receive a VBATT voltage. In addition, the low drop out (LDO) circuit 306 receives a transmit enable signal (designated “TX_EN”). When the transmit enable signal TX_EN is high, the low drop out (LDO) circuit 306 sends the power supply VCC to the power amplifier 302.
In the power supply control circuit 300 of FIG. 3 the output of the switcher 304 (designated “VSWITCHER”) is set to a direct current (DC) level that represents the peak level of VCC by the control signal VPEAK. A typical value for the VSWITCHER voltage for a GSM full power condition may be four and nine tenths volts (4.9 V). A typical value for the VPEAK voltage for a GSM full power condition may be one and six tenths volts (1.6 V) for a steady state operation. The wide bandwidth low drop out (LDO) circuit 306 is used for polar modulation envelope tracking and for providing a fast response to the reference control signal VRAMP.
FIG. 4 illustrates the timing waveforms 400 that would be expected for a low drop out (LDO) circuit 306 in a GSM (Global System for Mobile Communications) telecommunication device in which there are no load transient effects. FIG. 5 illustrates the timing waveforms 500 that occur when load transient effects are present.
As shown in FIG. 4 and in FIG. 5, the switcher enable signal ENSWITCHER is turned on in advance of the transmit enable signal TX_EN so that the value of the VSWITCHER signal has settled at its high value before the transmit enable signal TX_EN causes the low drop out (LDO) circuit 306 to send the power supply VCC to the power amplifier 302. The value of the VRAMP signal usually ramps up very quickly. For example, it may increase from a zero value to a maximum value in approximately five microseconds (5 μsec). This will cause the switcher load to go from a no load condition of zero milliamperes (0 mA) to a maximum load condition of approximately two amperes (2 A).
As shown in FIG. 5, this will cause a significant load transient in the VSWITCHER signal. The value of the VSWITCHER signal may temporarily decrease or “dip” as much as two hundred millivolts (200 mV). The time of the decrease is designated in FIG. 5 as TTRAN. The TTRAN value represents the time duration of the load transient. Because of the load transient the VCC signal will not be able to follow the VRAMP signal until the VSWITCHER value settles again after the end of the load transient. This is because the VCC signal is not able to follow the scaled VRAMP signal during the load transient because the VSWITCHER signal is less than the desired peak level scaled VPEAK during the load transient.
There is also an overshoot on the VSWITCHER value when the power amplifier 302 turns off. This is of no concern, however, because the low drop out (LDO) circuit 306 will force VCC to follow VRAMP as long as VSWITCHER has enough headroom.
Therefore, there is a need in the art for a system and method that is capable of providing a remedy for these prior art deficiencies. In particular, there is a need in the art for a system and method that is capable of providing an improved architecture for a power supply control circuit and a low drop out (LDO) circuit that suppresses load transients that are created by a radio frequency (RF) power amplifier (PA) turning on from an off state.